Present-day processors for digital signal processing (DSP) software algorithm computations in handsets, set-top boxes and other single device packages are struggling with the problem of accommodating the convergence of a wide variety of different real-time signal processing needs and control processing capabilities required to be handled in a single device. Such convergence of more and more features in a single device compounded with ever-evolving technology standards has led to exponentially increasing signal processing demand, creating new technology challenges. This is particularly true for mobile devices and for home network standards and different services, among other applications.
Existing technology choices for current System On Chip (SoC) design in emerging markets include the above mentioned DSP, General Purpose Processor (GPP) and Application Specific Integrated Circuit (ASIC) Block. Unfortunately, however, each of these falls short of fully solving the problem. While DSP is programmable for different applications and provides good real-time performance for DSP-centric algorithms, such as voice and data communications, DSP has limited control and general purpose processing capability. With GPP, again different applications are programmable, but with poor real-time performance and with the requirement for quite extensive control processing capability. As for the ASIC Block approach, while this may be optimized for specific application algorithms in terms of processing performance, this technique has very limited programmability and is usually not reusable for new applications, technologies and standards. To try to combine these three technological approaches, moreover, provides a trade-off near-impossibility (e.g. Qualcomm 3GMM Baseband—attempting to combine in a single SoC to meet the requirement with 2 DSPs+2 GPP's+13 ASIC accelerator blocks, for example). Such an approach, moreover, requires dedicated hardware for many possible features which hardware is not simultaneously exercised in such usage mode and still always takes up die area and consumes power.
The problems with current technologies as “solutions” reside in the fact that the systems become ever more complex, inflexible and costly, requiring more specialized cores that result in highly complex systems, with component and system scalability becoming an ever-pressing issue. New features, applications and standards, moreover, become harder to incorporate. More complex systems additionally mean longer development cycles and higher cost/performance ratios.
The present invention, indeed, as later fully explained, addresses the solution by providing a novel programmable core that can meet all the processing needs of the current device applications, which current processor architectures cannot accomplish, though the art is struggling with improvement proposals.
The advent of the pipeline processor, however, did significantly increase execution speed from CISC (Complicate Instruction Set Computer) to RISC (Reduced Instruction Set Computer). For an example of five instructions, CISC required 31 cycles to execute them in series; whereas the pipelined RISC provided a 350% improvement in throughput. Current deep-pipelined multi-issue DSP architecture followed with hardware added for pipelined implementation and functional units were created to increase parallelism of data flow with faster buses and increased clock rates. This has resulted, however, in increased complexity, larger die size and higher power consumption. But more importantly, as the emerging applications require more diverse signal processing algorithms, many are beyond that accommodated by conventional DSP technology—voice, audio, video image processing, data communication, etc. While the pipelined architecture improves the performance of a CPU, the pipeline solution loses its advantage when the order of calculations is different from the functional blocks aligned in a pipeline. In that case, calculation takes much longer. The pipeline solution is not always very efficient in operation, either. For instance, load and store instructions never use the stage for mathematical calculation. A specific pipeline, moreover, just cannot serve the needs of all algorithms—the exploding variety of real-time signal processing now desired in mobile and consumer devices, with current DSP and GPP techniques unable adequately to meet such emerging signal processing needs.
The present invention is believed to have provided a break-through solution through a programmable core and reconfigurable pipeline that admirably meets the processing needs of today's diverse applications through a novel combining of microprocessor-based technology developed for optimizing control programs based on fixed pipeline architectures, and switch fabric technology for the different field of telecommunication equipment, including internet routers/switches and embedded processors. The invention, indeed, combines the strengths of both CISC and RISC architectures, but surpasses the performance of current high-performance DSP cores, providing the programmability and flexibility of a general purpose processor and an architecture well-suited to a wide variety of processing needs, including communications algorithms, multimedia processing (audio, video, imaging), networking protocols, control functions and the like—in short, an application “agnostic” architecture for a “converged” world.